This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-345295, filed Nov. 9, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a technique of designing a semiconductor integrated circuit by CAD (computer aided design). More specifically, the invention relates to a method of evaluating a semiconductor integrated circuit to be designed in consideration of standby DC leakage current.
2. Description of the Related Art
In the design of a semiconductor integrated circuit by CAD, a threshold voltage of an FET has to be set in consideration of a tradeoff between reliability and performance (speed) of the circuit. In the case of an N-channel FET, standby current reduces due to a shift in threshold voltage in the positive direction under the influence of hot carriers. Though the reduction in standby current is preferable in terms of low power consumption, it lowers circuit performance, especially operation speed. In the case of a P-channel FET, a threshold voltage shifts in the direction that decreases the absolute value of the threshold voltage. If standby current increases as subthreshold current does, the circuit can be improved in performance or speed. However, there is fear that a semiconductor integrated circuit such as an IC and an LSI will not meet a value of the standby current required as the specifications of the circuit.
In the design of a semiconductor integrated circuit, therefore, the minimum initial threshold voltage that inhibits the speed from decreasing and satisfying an amount of standby current required as specifications has to be determined.
In the design of a semiconductor integrated circuit by CAD, conventionally, a value that is one-fourth of the total of channel widths of FETs in the circuit is used to determine the minimum threshold voltage of an N-channel FET. However, the value is estimated in accordance with the number of n-channel FETs in a CMOS inverter chain circuit and simply represented as an approximation. In order to produce more correct results, transistors to be cut off in standby mode should be detected and the total of channel widths of the transistors should be computed.
The problem of recent CMOS technology is that parasitic transistors are formed on a boundary between an active area and an element isolation region that gate electrodes of FETs cross and a threshold voltage is lowered by a trap of charges of the parasitic transistors. When a degree of integration was low, the influence of the above parasitic transistors was so small that it hardly became a problem. However, as the transistors decrease in size in accordance with an improvement in packing density, the influence of the parasitic transistors cannot be ignored.
There is case where a transistor having a great channel width (a large current driving capacity) has to be formed in a small space in order to actually form a pattern of a designed circuit. In this case, a multi-finger transistor is used as shown in FIG. 1. FIG. 1 is a pattern plan view schematically showing a structure of the multi-finger transistor (FET). In the multi-finger transistor, a gate insulation film is formed on an active area AA serving as source and drain regions, and gate polysilicon layers (fingers F1 to F3) are formed on the gate insulation film. Edges P1a, P1b, P2a, P2b, P3a and P3b are formed at intersections of a boundary between the active area AA and the element isolation region and the fingers F1 to F3.
As illustrated in FIG. 2, parasitic transistors Qpa and QPb are formed at their respective edges Pa and Pb at the intersections of the above boundary and the finger F. The parasitic transistors Qpa and QPb are connected in parallel with a main transistor Q. Even though the main transistor Q is cut off in standby mode, DC leakage current flow through current paths of the parasitic transistors Qpa and QPb.
Using a multi-finger transistor, it comes to have four or more edges (six edges in FIG. 1) on the actual pattern layout though it must have only two edges (parasitic transistors) on the circuit design. The analysis of leakage current due to such edges could not be conducted by the entire chip until now because there were no methods of counting huge numbers of edges of MOSFETs after the layout was completed.
Consequently, a large displacement is caused between a circuit and a pattern layout in the foregoing prior art evaluation method using approximation and estimation. It is thus likely that a semiconductor integrated circuit will not be correctly evaluated or a finished semiconductor integrated circuit will not meet the specifications of standby DC leakage current.
The above-described prior art method of evaluating a semiconductor integrated circuit decreases in precision and reliability since the evaluation is performed by approximation and estimation. The method is therefore desired to improve.
According to an aspect of the present invention, there is provided a method of evaluating a semiconductor integrated circuit, comprising a first block which simulates a circuit design value, the first block creating a file including a bias state of a MOSFET using a circuit simulator and an input file, a second block which extracts physical layout information from results of execution of LVS programs, and a third block which acquires final results by linking an output file of the first block and that of the second block to each other, the first block including inputting electric information of a schematic to a netlister and creating a netlist by the netlister, and performing a simulation by the circuit simulator using data of the netlist and an input stimulus and creating a file of simulation results, the second block including verifying whether data of a layout pattern and that of the schematic are equivalent to each other and creating a file of verification results, and creating a finger-model table file from the file of verification result in line with an actual pattern layout, and the third block including performing a circuit simulation in line with an actual pattern layout upon receiving the simulation results from the first block and the finger-model table file from the second block, and creating a result file by evaluation.